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Features
* * * * * * * * * *
850-930 MHz Output Frequency Rx Current: 14.5 mA Low Sleep Mode Current: 1 uA DSSS Processing and BPSK Modulation/Demodulation Battery Voltage Monitoring Circuitry 4 mW (6 dBm) Min. Transmit Power @ Vdd = 1.8V Serial Peripheral Interface (SPI) Control Power Supply Voltage Operating Range: 1.8V to 3.6V Low External Component Count 48QFN Package
Applications
* * * * * *
Low Band IEEE 802.15.4/ZigBeeTM-based Systems Industrial, Commercial, Home Lighting Control, Security, and HVAC Inventory Management Health Monitoring Wireless PC Peripherals such as Mouse, Keyboard, and Joystick Consumer Electronics Remote Controls and Toys
AT86RF210 Z-LinkTM Transceiver
868/902-928 MHz Direct Sequence Spread Spectrum BPSK Transceiver Preliminary
Description
The Atmel AT86RF210 Z-Link TM Transceiver is a fully integated, low-cost ZigBeeTM transceiver capable of transmitting and receiving BPSK modulated digital data over a frequency range of 868 MHz and 902-928 MHz using a minimum number of external components. It combines excellent RF performance with low cost, small size and low current consumption. The AT86RF210 includes a crystal stabilized Fractional-N synthesizer, BPSK transmitter and receiver, and full Direct Sequence Spread Spectrum Signal (DSSS) processing, including spreading and despreading. The device is fully compatable with IEEE 802.15.4 and ZigBee standards. It includes internal voltage regulation and battery monitoring circuitry and requires a minimum number of external support components. Figure 1. Block Diagram
Low Noise I/Q Mixer Amp Rx In Sw Out Ant In Sw In Tx Out Power Amp Data In Modulator Spreader SPI Bus SDO SDI SCLK SEL T/R Switch Synthesizer Despreader Data Out IF Amp Polyphase Filter Demodulator
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Figure 1. Functional Block Diagram
LNAOUT GND VDDA VSSA VDDD VSSD Reg Filter RSSI TEST RXD
Lim/PPF DC DIST
Despreader
SUB P P F M U X 1 Image Reject Filter P P F M U X 2 IQ-Limiter Strip 1.2 MHz CCA
LNAIN
LNA
BPSK Demod
1.200 MHz
LNAVSS RSWOUT VSS ANT VSS TSWIN FSK TUNE LOGIC
START
bandwidth Control Low Voltage Detect POR TXD
TR SW
/2 with Buffers
PPF AUTOCAL Circuit
VDD DBLR
NC
DC DIST/BG/PTAT with main BandGAP /N-M
VCO Fcx2
CHP_RDY S T A T U S
VSS PA OUT
PA
Fine Atten
PRGM DIV
Coarse Lock/Lock Detect Phase Detector Clock Distribution
Mode Logic
RESET_ RX TX CLK SEL
VSS BPSKO OK MOD
SDMOD
Tune Word
PA Regulator
FROM TXD
Cap Array
Spreader
Charge Pump
Xstal Osc
Serial Configruation Register
SCL SDO
PAREG
VCOREG
VCO
NC
NC
VCO VCO CPVCO CPOUT VSS TUNE
XTALGND
XTAL1
XTAL2
SDI
Table 1. Absolute Maximum Ratings*
Storage Temperature ..............................................-65 to +150 Maximum Input Voltage...........................................VDD + 0.5V Maximum Operating Voltage (VDD ) ................................... 4,5 *NOTE: Stresses beyond those listed in this table may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Operating Conditions
Symbol TAMB VSUPPLY HUMIDITY Note: Parameter Operating temperature Voltage supply range Humidity Min -40 1.8 10 2.7 Typ Max 85 3.6 90 Unit C V %
Unit operation is guaranteed by design when operating within these ranges.
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Table 3. DC Characteristics
Symbol IDDRX IDDTX IDDSleep VPOR VIH VIL VOH VOL Parameter Supply current, receive mode Supply current, transmit mode VDD = 3.3V Supply current, sleep mode Power-on reset voltage Digital input voltage high Digital input voltage low Digital output voltage high Digital output voltage low 0.7*VDD 0.3*VDD 0.7*VDD 0.3*VDD Min Typ 14.5 60 1 1.5 Max Unit mA mA uA V V V V V
Table 4. Receiver AC Characteristics
Symbol FLO ZRF Rx Sens Rx NF Rx P1dB Rx IP3 Rx LO Leakage Pin EDthresh Ttx/rx Trx/tx RJAMadj RJAMalt IFCF IFBW Imreg RX IFS/N Rx DR RSSI GN RSSI RG Parameter Local oscillator operating range, external inductor Port impedance antenna input Sensitivity, PER = 1% 40 kB/s, BW = 600 kHz BPSK modulation Receiver noise figure Receiver input 1dB compression point LNA gain max setting Input IP3 Receiver LO leakage (all possible paths) Maximum input signal; LNA gain min setting Default energy detection threshold (programmable) Turnaround time, transmit to receive Turnaround time, receive to transmit Receiver relative jamming resistance adjacent channel (desired signal = -89 dBm) Receiver relative jamming resistance alternate channel (desired signal = -89 dBm) IF center frequency IF bandwidth IF image rejection RX IF SNR (600 KHz BW) Min input signal = -100 dBm Receiver max data rate RSSI Gain RSSI RANGE -105 0 30 1.2 600 -35 10 40 1.0 -30 -84 100 100 Min 850 50 -95 6.0 -40 -30 -80 -20 Typ Max 930 Unit MHz Ohm dBm dB dBm dBm dBm dBm dBm usec usec dB dB MHz KHz dB dB Kb/s uA/dB dBm
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Table 5. Transmitter AC Characteristics
Symbol Tx Pout Parameter Transmitter output power: Vdd = 1.8V Vdd = 3.6V Tx symbol rate 915 MHz band Tx symbol rate 868 MHz band Transmit error vector magnitude measured over 1000 chips Transmit power spectral density 915 MHz band; |f-fc| >1.2 MHz (absolute measured in 100 KHz resolution BW) Transmitter power variation over temperature Antenna switch impedance Transmit spurious within 2 MHz Transmit spurious beyond 2 MHz Transmitter power control resolution Transmitter power control range Transmitter low-voltage threshold Transmitter low-voltage output power Transmitter turn-on time 90% full power Transmitter turn-off time less than 10% of output power 1.8 0.25 10 10 0.25 25 1.9 0.50 3 50 -25 -35 0.75 40 20 35% -20 dBm Min Typ 6 12 Kbit/s Kbit/s Max Unit dBm
Rsym Rsym EVM PSD
Tx Pvar Tx/Rx Z Tx spur Tx spur Tx Pcon Tx Pran Tx lvt Tx lvpo Tx tot Tx tofft
dB Ohm dBc dBc dB dB Volt mwatt usec usec
Table 6. Synthesizer AC Characteristics
Symbol F LO LOPN Fpull Lopno TXtal TSynth Synthres Parameter Carrier frequency LO phase noise (integrated 10 Hz-100 KHz rms) Crystal oscillator frequency pulling @ 25C Local oscillator phase noise 2.0 MHz offset from LO Crystal oscillator settling time Phase locked loop settling time Synthesizer tuning resolution 500 Min 850 6 20 -95 150 100 Typ Max 930 Unit MHz deg ppm dBc usec usec Hz
. Table 7. Serial Configuration Register*
Symbol TRISE TFALL TCLKS Parameter CMOS input rise time CMOS input fall time CLK setup time 25 Min Typ 20 20 Max Unit nsec nsec nsec
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Table 7. Serial Configuration Register* (Continued)
Symbol TCLKH TCLKW TSDIS TSDIH TSDOD Note: Parameter CLK hold time CLK pulse width SDI setup time SDI hold time SDO delay time Min 25 50 25 25 25 Typ Max Unit nsec nsec nsec nsec nsec
*Rise and fall time is measured 10%-90%. Delay, setup, and hold times are measured 50%-50%
Table 8. Low Battery Detector Characteristics
Symbol Lvbat 0 Parameter Low voltage battery detector threshold voltage mode 0 (5 bit resolution) Min 1.5 Typ Max 3.5 Unit Volt
Table 9. Preliminary PIN Description QFN48
PIN SUB LNARFIN LNAVSS RSWOUT VSS ANT VSS TSWIN PAOUT VSS VDDA PAREG VCOVDD VCOREG No Connect No Connect VCOVSS VCOTUNE Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A_I/O A_I V_I A_O V_I V_I NA NA NA NA NA NA NA NA Type V_I/O RF_I RF_I/O RF_I/O RF_I/O RF_I/O RF_I/O RF_I/O RF_I/O Startup Cond GND NA NA NA NA NA NA NA NA Description Substrate connection Low-noise amplifier RF input Analog ground for the LNA Transmit-receive switch out. Signal from ANT is routed through the TR switch to the LNA input. Transmit-receive switch isolation ground 1. Antenna RF input/output. Nominal impedance 50, part of T/R switch. Routes signal to the LNA or from the PA. Transmit-receive switch isolation ground 2. Transmit-receive switch input. Signal from PA comes into TR switch and is routed to ANT. PA signal routed into the T/R switch from the PA. Pin not used Secondary analog power supply input. Set in proximity to power amplifier circuits. PA regulator output. Settable current source output for charging a large external capacitor during battery operation. VCO power supply input External filter cap for the VCO regulator Pin not used Pin not used VCO power supply ground LO VCO control input. An internal differential varactor diode tunes the LO frequency. The control voltage should be referenced to LOGND.
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Table 9. Preliminary PIN Description QFN48 (Continued)
PIN CPOUT CPVSS CPVDD XTAL1 XTAL2 Num 19 20 21 22 23 Type A_I A_I/O V_I A_I A_I Startup Cond NA NA NA NA NA Description Charge pump output Analog synthesizer ground Analog synthesizer power supply Crystal oscillator input 1. One side of oscillator crystal is connected to this pin. Crystal oscillator input 2. When internal oscillator is used, this pin has crystal connected. When external clock is used, the external clock is input on this pin. Crystal oscillator ground Transmit data input from the controller Pin not used Serial data input Input to configuration data shift register. Data accepted at the rising edge of SCL. Output from configuration data shift register. Data changes at the falling edge of SCL. Serial data clock SPI slave select line Clock output to controller. Can be divided by 1 to 16. Mode control input. TX HIGH with RX LOW causes chip to go to transmit. Mode control input. RX HIGH with TX LOW causes chip to go to receive mode. Digital power supply input Digital power supply ground. Oscillator start. A transition on this pin will start the internal oscillator. A low on this pin allows the part to run from an external clock. Chip ready. Handshake signal between the controller and the chip. Also acts as fault interrupt. Digital data from demodulator Pin not used Pin not used Pin not used V_I/O A_0 D_IO D_O TBD LOW VDD Filter cap for internal low dropout regulator for poly phase filter Logarithmic detection current Test pin. Enables nand tree test or scan test. Clear channel assessment. Digital signal indicates when channel activity is above a programmable threshold.
XTALVSS TXDAT No Connect SDI
24 25 26 27
A_I/O D_I D_I D_I
NA HIGH LOW NA
SDO SCLK SEL SYSCLK TX RX VDDDIG VSSDIG START CHPRDY RXDOUT No Connect No Connect No Connect PPFREG RSSI XTALMODE CCA
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
D_O D_I D_I D_O D_I D_I V_I V_I/O D_I D_O D_O
NA NA HIGH HIGH HIGH HIGH NA NA HIGH LOW NA NA NA
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Table 9. Preliminary PIN Description QFN48 (Continued)
PIN VDDA VSSA LNAOUT Num 46 47 48 Type V_I V_I/O A_I/O Startup Cond NA GND Description Analog (RF) power supply input Analog (RF) power supply ground LNA external inductor. Collector inductor for LNA. P/O RF tuning network.
I/O Table Notes
* * * * * * * *
RF_I RF_I/O Voltage_I/O V_I A_I A_O D_I D_O
RF input RF input/output Voltage input/output Voltage input Analog input Analog output Digital input Digital output
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Figure 2. Typical ZigBee Application Schematic
This is a sample application schematic for RF210 (The pinout and component values are preliminary)
Receiver Tuning
C10 TBD L0 TBD C14 100p C13 10n R0 TBD
V_BAT
C23 10n
43 RSSI
44 XTALMODE
42 PPFREG
X X
40 No Connect 39 No Connect
46 VDDA
45 CCA
41 No Connect
38 RXDOUT
37 CHPRDY
48 LNAOUT
47 VSSA
VDD
Receiver Matching
1 SUB L1 TBD C17 TBD C15 TBD C18 100P 2 LNARFIN 3 LNAVSS 4 RSWOUT
CCA_IN 36 START 35 VSSDIG 34 VDDDIG 33 RX C1 100p C0 10n RSSI_ANALOG START
(DIGITAL INTERFACE)
X
RX_DATA CHP_RDY
(RF INTERFACE)
5 VSS 6 ANT
32 TX 31 SYSCLK 30 SELl 29 SCLK 28 SDO 27 SDI
PA Matching
C19 TBD L2 TBD C22 TBD L6 TBD
7 VSS 8 TSWIN 9 PAOUT
AT86RF210 Z-Link Transceiver
x
RX TX SPI_SEL SPI_CLK SPI_OUT
X
10 VSS 11 VDDA 12 PAREG (FREQUENCY GENERATION INTERFACES)
26 No connect 25 TXDAT
x X
SPI_IN TX_DAT_P SYS_CLK_OUT
15 No connect
16 No connect
14 VCOREG
17 VCOVSS
19 CPOUT
22 XTAL1
23 XTAL2
C20 250u
21 CPVDD
24 XTALVSS
13 VCOVDD
20 CPVSS
C21 100p
18 VCOTUNE
VSS
Optional
C9 100p C8 10n C7 TBD C6 TBD
X X
R2 TBD C5 TBD C4 TBD R1 TBD C2 100p
Loop Filter
C3 10n
Atmel RF Design Cent.
Note: With pin 44 (Xstal_Sel) low RF210 uses system clock from controller With pin 44 (Xstal_Sel) high RF210 uses external crystal placed across pin 22 & 23
9/9/03
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Z-Link ZigBee Controller
(DIGITAL INTERFACE)
AT86RF210
Package Drawing
48QFN
D A A3
Index Area
E
A2
A1
Top View
L
Side View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM 7.00 BSC 7.00 BSC 2.25 2.25 0.80 0.0 0.0 4.70 4.70 0.90 0.02 0.65 0.20 REF 0.30 0.40 0.50 BSC 0.18 0.23 0.30 2 0.50 5.25 5.25 1.00 0.05 1.00 MAX NOTE
D2
D E D2
E2
E2 A A1
b e Pin 1
A2 A3 L
Bottom View
e b
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VKKD-2, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
12/10/02 TITLE 2325 Orchard Parkway 48QN1, 48-lead 7.0 x 7.0 mm Body, 0.50 mm Pitch, Quad Flat San Jose, CA 95131 No Lead Package (QFN) DRAWING NO. 48QN1 REV. A
R
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(c) Atmel Corporation 2003. All rights reserved. Atmel(R) and combinations thereof are registered trademarks and Z-Link TM is a trademark of Atmel Corporation or its subsidiaries. ZigBee TM is a trademark of the ZigBee Alliance. Other terms and product names may be the trademarks of others.
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5033AS-WIRE-10/03

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